CY7C1329-100AC

CY7C1329-100AC, synchronous-pipelined cache SRAM, –0.5 V to +4.6 V, 20 mA, TQFP, Cypress Semiconductor

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Price:: US $5.10~5.43 / piece [Get Latest Price]

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Qty (lots)	Price/lot
100 ~ 500 :	5.43 / Piece
500 ~ 1000 :	5.25 / Piece
1000 ~ 1500 :	5.10 / Piece

PartNumber:: CY7C1329-100AC

Brand:: Cypress Semiconductor - Cypress | Pack: TQFP | D/C: 01+

Availability:: Supply Ability: 10000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2013-10-25

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Part Number:CY7C1329-100AC
US $5.10 - 5.43
Quantity:

piece

Product Summary

The CY7C1329-100AC is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM. The CY7C1329-100AC is designed to support zero wait state secondary cache with minimal glue logic. The CY7C1329-100AC pins can operate at either the 2.5V or the 3.3V level. The I/O pins of the CY7C1329-100AC are 3.3V tolerant when VDDQ=2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max-imum access delay from the clock rise is 3.5 ns (166-MHz device). The CY7C1329-100AC supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC.

Parametrics

CY7C1329-100AC absolute maximum ratings: (1)Storage Temperature: –65 to +150 ℃; (2)Ambient Temperature with Power Applied: –55 to +125 ℃; (3)Supply Voltage on VCC to Relative GND[2]: –0.5 V to +4.6 V; (4)DC Voltage Applied to Outputs[2] in High Z State: –0.5 V to VCC + 0.5 V; (5)DC Input Voltage[2]: –0.5 V to VCC + 0.5 V; (6)Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage: ＞2001V; (8)Latch-Up Current: ＞200 mA.

Features

CY7C1329-100AC features: (1)Supports 133-MHz bus for Pentium and PowerPC; (2)operations with zero wait states; (3)Fully registered inputs and outputs for pipelined operation; (4)64K × 32 common I/O architecture; (5)Single 3.3V power supply; (6)Fast clock-to-output times; (7)User-selectable burst counter supporting Intel; (8)Pentium interleaved or linear burst sequences; (9)Separate processor and controller address strobes; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)JEDEC-standard 100 TQFP pinout; (13)“ZZ” Sleep Mode option and Stop Clock option.