A1240A-PQ144C

Product Summary

The A1240A-PQ144C is a field programmable gate array (FPGA). The A1240A-PQ144C presents a two-module architecture, consisting of C-modules and Smodules. The A1240A-PQ144C is optimized for both combinatorial and sequential designs. Based on Actels patented channeled array architecture, the A1240A-PQ144C provides significant enhancements to gate density and performance while maintaining downward compatibility with the ACT 1 design environment and upward compatibility with the A1240A-PQ144C design environment. The A1240A-PQ144C is implemented in silicon gate, 1.0-μm, two-level metal CMOS, and employ Actels PLICE antifuse technology. This revolutionary architecture offers gate array design flexibility, high performance, and fast time-to-production with user programming. The A1240A-PQ144C is supported by the Designer and Designer Advantage Systems, which offers automatic pin assignment, validation of electrical and design rules, automatic placement and routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are supported on the following platforms: 386/486 PC, Sun, and HP workstations. The systems provide CAE interfaces to the following design environments: Cadence, Viewlogic, Mentor Graphics, and OrCAD.

Parametrics

A1020B-PL84C absolute maximum ratings: (1)VCC DC supply voltage: -0.5 to +7.0 V; (2)VI Input voltage: -0.5 to VCC + 0.5 V; (3)VO Output voltage: -0.5 to VCC + 0.5 V; (4)IIO I/O source sink current2: 20 mA; (5)TSTG Storage temperature: -65 to +150 °C.

Features

A1240A-PQ144C features: (1)Up to 8,000 Gate Array Gates (20,000 PLD equivalent gates); (2)Replaces up to 200 TTL Packages; (3)Replaces up to eighty 20-Pin PAL Packages; (4)Design Library with over 500 Macro Functions; (5)Single-Module Sequence Functions; (6)Wide-Input Combinatorial Functions; (7)Up to 1,232 Programmable Logic Modules; (8)Up to 998 Flip-Flops; (9)Datapath Performance at 105 MHz; (10)16-Bit Accumulator Performance to 39 MHz; (11)Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz; (12)Two High-Speed, Low-Skew Clock Networks; (13)I/O Drive to 10 mA; (14)Nonvolatile, User Programmable; (15)Logic Fully Tested Prior to Shipment; (16)1.0 micron CMOS Technology.

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Diagrams