Product Summary

The AD568JQ is an ultrahigh-speed, 12-bit digital-to-analog converter (DAC) settling to 0.025% in 35 ns. The monolithic device AD568JQ is fabricated using Analog Devices Complementary Bipolar (CB) Process. This is a proprietary process featuring high-speed NPN and PNP devices on the same chip without the use of dielectric isolation or multichip hybrid techniques. The high speed of the AD568JQ is maintained by keeping impedance levels low enough to minimize the effects of parasitic circuit capacitances. The DAC AD568JQ consists of 16 current sources configured to deliver a 10.24 mA full-scale current. Multiple matched current sources and thin-film ladder techniques are combined to produce bit weighting.

Parametrics

AD568JQ absolute maximum ratings: (1)vcc to refcom: 0 v to +18 v; (2)vee to refcom: 0 v to –18 v; (3)refcom to lcom: +100 mv to –10 v; (4)acom to lcom: ±100 mv; (5)thcom to lcom: ±500 mv; (6)spans to lcom: ±12 v; (7)ibpo to lcom: ±5 v; (8)iout to lcom: –5 v to vth; (9)digital inputs to thcom: –500 mv to +7.0 v; (10)voltage across span resistor: 12 v; (11)vth to thcom: –0.7 v to +1.4 v; (12)logic threshold control input current: 5 ma; (13)power dissipation: 100 mw; (14)storage temperature range, q (cerdip) package: –65℃ to +150℃; (15)junction temperature: 175℃; (16)thermal resistance: θja: 75℃/w; θjc: 25℃/w.

Features

AD568JQ features: (1)Ultrahigh Speed: Current Settling to 1 LSB in 35 ns; (2)High Stability Buried Zener Reference on Chip; (3)Monotonicity Guaranteed Over Temperature; (4)10.24 mA Full-Scale Output Suitable for Video Applications; (5)Integral and Differential Linearity Guaranteed Over Temperature; (6)0.3" “Skinny DIP” Packaging; (7)Variable Threshold Allows TTL and CMOS Interface; (8)MIL-STD-883 Compliant Versions Available.

Diagrams

AD568JQ functional block diagram

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