Product Summary
The SN74ABT162601DLR is an 18-bit universal bus transceiver. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-W series resistors to reduce overshoot and undershoot.
Parametrics
SN74ABT162601DLR absolute maximum ratings: (1)Supply voltage range, VCC: –0.5 V to 7 V; (2)Input clamp current, IIK: -18 mA; (3)Output clamp current, IOK: -50 mA; (4)Voltage range applied to any output in the high or power-off state, VO: -0.5 V to 5.5 V; (5)Current into any output in the low state, IO: 128 mA; (6)Package thermal impedance: 81°C/W; (7)Storage temperature range: -65°C to 150°C.
Features
SN74ABT162601DLR features: (1)Members of the Texas Instruments WidebusE Family; (2)B-Port Outputs Have Equivalent 25-W Series Resistors, So No External Resistors Are Required; (3)State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation; (4)UBT E (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode; (5)Latch-Up Performance Exceeds 500 mA Per JESD 17; (6)Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C; (7)High-Impedance State During Power Up and Power Down; (8)Flow-Through Architecture Optimizes PCB Layout; (9)Package Options Include Plastic 300-mil, Shrink Small-Outline (DL) and Thin Shrink, Small-Outline (DGG) Packages and 380-mil, Fine-Pitch Ceramic Flat (WD) Package, Using 25-mil Center-to-Center Spacings.
Diagrams
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![]() Universal Bus Functions 18bit univ Bus |
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![]() Gates (AND / NAND / OR / NOR) Quad 2-input Positive-NAND gates |
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![]() SN7400DG4 |
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![]() SN7400DRE4 |
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![]() IC QUAD 2IN POS-NAND GATE 14SOIC |
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