CY7C1380D-167AXC

CY7C1380D-167AXC, Pipelined SRAM, –0.5 V to +4.6 V, 20 mA, TQFP, Cypress Semiconductor

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Price:: US $11.99~12.33 / piece [Get Latest Price]

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Qty (lots)	Price/lot
100 ~ 500 :	12.33 / Piece
500 ~ 1000 :	12.17 / Piece
1000 ~ 1500 :	11.99 / Piece

PartNumber:: CY7C1380D-167AXC

Brand:: Cypress Semiconductor - Cypress | Pack: TQFP | D/C: 08+

Availability:: Supply Ability: 10000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2013-10-27

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Part Number:CY7C1380D-167AXC
US $11.99 - 12.33
Quantity:

piece

Product Summary

The CY7C1380D-167AXC is a Pipelined SRAM. The CY7C1380D-167AXC integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous of the CY7C1380D-167AXC inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous of the CY7C1380D-167AXC inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous of the CY7C1380D-167AXC inputs include the Output Enable (OE) and the ZZ pin.

Parametrics

CY7C1380D-167AXC absolute maximum ratings: (1)Storage Temperature: –65 to +150 ℃; (2)Ambient Temperature with Power Applied: –55 to +125 ℃; (3)Supply Voltage on VCC to Relative GND[2]: –0.5 V to +4.6 V; (4)DC Voltage Applied to Outputs[2] in High Z State: –0.5 V to VDDQ+0.5 V; (5)DC Input Voltage[2]: –0.5 V to VDD+0.5 V; (6)Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage: ＞2001V; (8)Latch-Up Current: ＞200 mA.

Features

CY7C1380D-167AXC features: (1)Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P, and MCM63Z736; (2)Supports 166-MHz bus operations with zero wait states; (3)Internally self-timed output buffer control to eliminate the need to use OE; (4)Fully registered (inputs and outputs) for pipelined operation; (5)Byte Write capability; (6)128K × 36 common I/O architecture; (7)Single 3.3V power supply; (8)Fast clock-to-output times: 3.5 ns; (9)Clock Enable (CEN) pin to suspend operation; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)JEDEC-standard 100 TQFP package; (13)Burst Capability—linear or interleaved burst order; (14)Low standby power.