EPM7032SLC44-10

Product Summary

The EPM7032SLC44-10 is a high-density, high-performance PLD. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. It supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. It provides programmable speed/power
optimization. Speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power.

Parametrics

EPM7032SLC44-10 absolute maximum ratings: (1)Supply voltage: -2.0 to 7.0 V; (2)DC input voltage: -2.0 to 7.0 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature No bias: -65 to 150 ° C; (5)Ambient temperature Under bias:–65 to 135 ° C; (6)Junction temperature: +150 °C.

Features

EPM7032SLC44-10 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in AX 7000S devices; (3)ISP circuitry compatible with IEEE Std. 1532; (4)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (5)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (7)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (8)PCI-compliant devices available; (9)Open-drain output option in MAX 7000S devices; (10)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (11)Programmable power-saving mode for a reduction of over 50% in each macrocell; (12)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (13)44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages; (14)Programmable security bit for protection of proprietary designs; (15)3.3-V or 5.0-V operation.

Diagrams