SC26C562C1A

SC26C562C1A, single-chip CMOS-LSI communication device, 7.0 V, 8 bits, 64 K, PLCC

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Price:: US $0.15~2.74 / piece [Get Latest Price]

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Qty (lots)	Price/lot
100 ~ 500 :	2.74 / Piece
500 ~ 1000 :	1.62 / Piece
1000 ~ 1500 :	0.15 / Piece

PartNumber:: SC26C562C1A

Brand:: Philips Electronics India Limited - PHILIPS | Pack: PLCC | D/C: 01+

Availability:: Supply Ability: 10000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Total Price:: US $0

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Products Upload time: 2013-07-05

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Part Number:SC26C562C1A
US $0.15 - 2.74
SC26C562C1A

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Product Summary

The SC26C562C1A is a single-chip CMOS-LSI communication device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SC26C562C1A interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The SC26C562C1A (CDUSCC) is (PIN) hardware and (REGISTER) software compatible with the existing SC26C562C1A (DUSCC). CDUSCC will automatically configure to the NMOS DUSCC register map (default mode) on power up.

Parametrics

SC26C562C1A absolute maximum ratings: (1)TA, operating ambient temperature2: 0 to +70 °C; (2)TSTG, storage temperature: -65 to +150 °C; (3)VCC, voltage from VCC to GND3: –0.5 to +7.0 V; (4)VS, voltage from any pin to ground3: –0.5 to VCC +0.5 V.

Features

SC26C562C1A features: (1)Dual full-duplex synchronous/ asynchronous receiver and transmitter; (2)Multi-protocol operation: BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc; COP: Single SYNC, dual SYNC, BiSYNC, DDCMP; ASYNC: 5-8 bits plus optional parity; (3)Sixteen character receive and transmit FIFOs with interrupt threshold control; (4)Watchdog timer; (5)0 to 10 Mbit/sec data rate; (6)Programmable bit rate for each receiver and transmitter selectable from: 19 fixed rates: 50 to 64K baud; One user-defined rate derived from programmable counter/timer; External 1X or 16X clock; Digital phase-locked loop; (7)Parity and FCS (frame check sequence LRC or CRC)generation and checking; (8)Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1, Manchester; (9)Programmable channel mode: full- or half-duplex, auto-echo, or local loopback.