SN74ABT16374ADLR

SN74ABT16374ADLR, 16-bit edge-triggered d-type FLIP-FLOP, -18 mA, 89°C/W, SSOP

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Price:: US $0.82~0.97 / piece [Get Latest Price]

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Qty (lots)	Price/lot
100 ~ 500 :	0.97 / Piece
500 ~ 1000 :	0.90 / Piece
1000 ~ 1500 :	0.82 / Piece

PartNumber:: SN74ABT16374ADLR

Brand:: Texas Instruments - TI | Pack: SSOP | D/C: 00+

Availability:: Supply Ability: 10000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-09-09

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Part Number:SN74ABT16374ADLR
US $0.82 - 0.97
Quantity:

piece

Product Summary

The SN74ABT16374ADLR is a 16-bit edge-triggered d-type FLIP-FLOP. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state.

Parametrics

SN74ABT16374ADLR absolute maximum ratings: (1)Supply voltage range, VCC: –0.5 V to 7 V; (2)Input clamp current, IIK: -18 mA; (3)Output clamp current, IOK: -50 mA; (4)Voltage range applied to any output in the high or power-off state, VO: -0.5 V to 5.5 V; (5)Current into any output in the low state, IO: 128 mA; (6)Package thermal impedance: 89°C/W; (7)Storage temperature range: -65°C to 150°C.

Features

SN74ABT16374ADLR features: (1)Members of the Texas Instruments WidebusE Family; (2)State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation; (3)ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; (4)Latch-Up Performance Exceeds 500 mA Per; (5) EDEC Standard JESD-17; (6)Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C; (7)High-Impedance State During Power Up and Power Down; (8)Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise; (9)Flow-Through Architecture Optimizes PCB Layout; (10)High-Drive Outputs (–32-mA IOH, 64-mA IOL); (11)Package Options Include Plastic 300-mil; (12)Shrink Small-Outline (DL) and Thin Shrink; (13)Small-Outline (DGG) Packages and 380-mil; (14)Fine-Pitch Ceramic Flat (WD) Package; (15)Using 25-mil Center-to-Center Spacings.