CY7C1380C-167AC

CY7C1380C-167AC, Pipelined SRAM, –0.5 V to +4.6 V, 20 mA, TQFP, Cypress Semiconductor

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Price:: US $14.80~15.11 / piece [Get Latest Price]

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Qty (lots)	Price/lot
100 ~ 500 :	15.11 / Piece
500 ~ 1000 :	14.95 / Piece
1000 ~ 1500 :	14.80 / Piece

PartNumber:: CY7C1380C-167AC

Brand:: Cypress Semiconductor - Cypress | Pack: TQFP | D/C: 05+

Availability:: Supply Ability: 10000/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-10-27

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Part Number:CY7C1380C-167AC
US $14.80 - 15.11
Quantity:

piece

Product Summary

The CY7C1380C-167AC is a Pipelined SRAM. The CY7C1380C-167AC integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous of the CY7C1380C-167AC inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous of the CY7C1380C-167AC inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous of the CY7C1380C-167AC inputs include the Output Enable (OE) and the ZZ pin.

Parametrics

CY7C1380C-167AC absolute maximum ratings: (1)Storage Temperature: –65 to +150 ℃; (2)Ambient Temperature with Power Applied: –55 to +125 ℃; (3)Supply Voltage on VCC to Relative GND[2]: –0.5 V to +4.6 V; (4)DC Voltage Applied to Outputs[2] in High Z State: –0.5 V to VDDQ+0.5 V; (5)DC Input Voltage[2]: –0.5 V to VDD+0.5 V; (6)Current into Outputs (LOW): 20 mA; (7)Static Discharge Voltage: ＞2001V; (8)Latch-Up Current: ＞200 mA.

Features

CY7C1380C-167AC features: (1)Supports bus operation up to 250 MHz; (2)Available speed grades are 250, 225, 200,166 and 133MHz; (3)Registered inputs and outputs for pipelined operation; (4)3.3V core power supply; (5)2.5V / 3.3V I/O operation; (6)Fast clock-to-output times: 2.6 ns; (7)Provide high-performance 3-1-1-1 access rate; (8)User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences; (9)Separate processor and controller address strobes; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)Single Cycle Chip Deselect; (13)Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages; (14)IEEE 1149.1 JTAG-Compatible Boundary Scan; (15)“ZZ” Sleep Mode Option.